FPM, EDO, and Synchronous DRAM Technologies

Introduction

Cette page parle en gros du concept de DRAM et compare brièvement les technologies Fast Page Mode, Extended Data Out, et Synchronous DRAM .

Concepts Generaux DRAM

"DRAM" is an acronym for "Dynamic Random Access Memory." "Dynamic" indicates that for the memory chip to remember data, the memory chip requires every bit to be refreshed within a certain time period. When power is removed from a DRAM, the data is lost. "Random Access" indicates that each cell in the memory chip can be read or written in any order. This contrasts to a sequential memory device where data must be read or written in a certain order. For example, a disk employs random access, while a cassette tape employs sequential access.

The bits of a DRAM are arranged in cells where each cell contains a specific number of bits. For example, a 4 MB x 4 Bit DRAM has four bits per cell. The cells of a DRAM are arranged like a spreadsheet and accessed by a row address and a column address. A typical DRAM access starts by specifying a row address, then specifying a column address. Next, a signal is pulled active or non-active to determine if the access is a read or a write. Then the DRAM places the data from the cell on the data output if the access is a read; or, the DRAM writes the data from the data inputs into the cell if the access is a write.

Fast Page Mode (FPM) DRAMs

Fast Page Mode DRAMs are currently the most-used category of DRAMs. FPM DRAMs are faster than previous generation DRAMs through the ability to work within a page.

A page is described as the section of memory available within a row address. Within one specific row are several columns of memory bits. With FPM DRAMs, you need only specify the row address once for accesses within the same page addresses. Successive accesses to the same page of memory only require a column address to be selected, which saves time in accessing the memory. JEDEC, the electronic standards agency, has specified standards for the FPM DRAM.

Extended Data Out (EDO) DRAMs

Extended Data Out DRAMs work very similar to FPM DRAMs. EDO DRAMs have the ability to work within a page like FPM DRAMs. The primary advantage with EDO DRAMs over FPM DRAMs is that EDO DRAMs hold the data valid even after the signal that "strobes" the column address goes inactive. This allows faster microprocessors to manage time more efficiently, performing many tasks without having to attend to slower memory. That is, while the EDO DRAM is retrieving an instruction for the microprocessor, the microprocessor can perform other tasks without worrying that the data will become invalid. JEDEC has specified standards for the EDO DRAM.

Synchronous DRAM (SDRAM)

With the introduction of faster microprocessors, FPM and EDO DRAMs signal-controlled operation has become a bottleneck. The most efficient memory is that which runs at the same speed as the microprocessor. That is, FPM and EDO DRAMs rated in 60, 70, and 80 ns were fast enough to keep up with microprocessors slower than 66 MHz; however, with the introduction of 66 MHz and faster microprocessors, the need for a faster memory standard was necessary. JEDEC, the electronic standards agency, subsequently developed the Synchronous DRAM standard.

SDRAMs work completely different from FPM and EDO DRAMs. FPM and EDO DRAMs are driven by pulling signals active whereas SDRAMs inputs and outputs its data synchronized to a externally-supplied clock. The use of a clock allows for extremely fast consecutive read and write capability over FPM and EDO DRAMs.

Signal propagation delays, i.e., the time from when the input signals are applied to when the output signals become valid, are the main speed consideration with FPM and EDO DRAMs; therefore, FPM and EDO DRAMs are measured in nanoseconds (ns). The clock is the main speed consideration with SDRAMs; therefore, SDRAMs are measured in megahertz (MHz). Also, while SDRAMs have some signals with the same names as those on FPM and EDO DRAMs, the signals operate differently.

To work with up to 100 MHz clock speeds, SDRAMs are designed with two internal banks. This allows one bank to get ready for access while the other bank is being accessed. Sometimes this two bank feature is reflected in the description of the SDRAM. For example, a 16 MB SDRAM may be described as a 1 MB x 8 bit x 2 banks, where as the equivalent 16 MB FPM or EDO DRAM is described as a 2 MB x 8 bit.

Conclusion

With faster microprocessors outrunning FPM speeds, EDO is a faster solution. The most efficient memory, however, is that which runs at the same speed as the microprocessor, i.e. SDRAM. SDRAMs are projected to become the most-used category of DRAMs in the future for high-speed computers.

Simple Technology is a trademark of Simple Technology, Inc. All other trademarks and product names are the property of their respective companies.